It is well known that programmable frequency dividers are commonly used in phase-lock-loop (PLL) frequency synthesizers, such as for generating a local oscillating signal in a receiver or a carrier signal in a transmitter. One conventional type of programmable frequency divider is a phase-switching-type frequency divider which includes a) a prescaler which divides the frequency of an input waveform,f.sub.in, by two, b) a divide-by-two circuit which divides the frequency of the prescaler output by two and outputs four phase-offset versions of f.sub.in /4- offset by 0.degree., 90.degree., 180.degree., and 270.degree. respectively, c) a multiplexer for selectively switching between the four outputs of the divide-by-two circuit, d) a divide-by-N circuit for dividing the frequency of the waveform output by the multiplexer by N, e) a pulse generator for generating K pulses per output cycle of the frequency divider, f) a four-state counter for incrementing after each pulse of the pulse generator, and g) a decoder for controlling the multiplexer based on the four-state counter output. To swallow one cycle of f.sub.in and thereby increase the division factor of the frequency divider by one, the multiplexer switches to an output of the divide-by-two circuit which lags the previously selected output by 90.degree.. If the decoder controls the multiplexer to switch to a 90.degree. lagging output K times per output cycle of the frequency divider, i.e., each time the counter increments, K input cycles are swallowed and the division factor becomes 4N+K To achieve programmability, the pulse generator must be able to generate various numbers of pulses each output cycle, depending on K. Designing and programming such a pulse generator is complicated. Also, for large values of K, the pulse generator, the divide-by-four counter, and the decoder must operate at high frequencies, thereby increasing power consumption.